Network Engineer, High-Speed Interconnects (ML Infrastructure)
xAI · Palo Alto, CAOverview
You will design and optimize high-speed copper and optical network interconnects for massive AI training and inference clusters at xAI.
Skills
Responsibilities
- Design and validate high-speed copper and optical connectivity solutions for AI clusters
- Own vendor due diligence and onboarding for 1.6T products and optical transceivers
- Evaluate early co-packaged and near-packaged engines for switches and GPUs
- Collaborate with ML training teams to translate workload communication patterns into topology requirements
- Drive failure analysis and root cause for interconnect-related production issues
Requirements
- Deep expertise in high-speed interconnect technologies for large-scale AI clusters
- Experience with physical layer and system-level integration of copper and optical interconnects
- Knowledge of 200G+ SerDes, PAM4, photonics, and signal integrity
About xAI
xAI builds the Super Intelligence stack, including Colossus supercomputers and Grok models.
What to prepare
Full job post · as written by xAI
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today, SpaceX is actively developing the technologies to make this possible, with the ultimate goal of making life multiplanetary and expanding consciousness to the stars.
SpaceXSI is building Super Intelligence to help humanity understand the universe. Our teams are building the full Super Intelligence stack: from our Colossus supercomputers, to Grok models, to our suite of applications, including Grok Bot, Grok Build, Grok Imagine, Grok Voice, and X. We're creating a powerful flywheel where more compute trains better models, better models power more useful products, and what we learn from people using those products shapes what we build next.
NETWORK ENGINEER, HIGH-SPEED INTERCONNECTS (ML INFRASTRUCTURE)
SpaceXSI is building at a furious pace with the latest compute and switching hardware to help people understand the universe. We are looking for exceptional ML Infrastructure Engineers with deep expertise in high-speed interconnect technologies to design, build, and optimize the network fabric that powers large-scale AI training and inference clusters. This strategic role will drive innovation in high-bandwidth, low-latency, power-efficient interconnects critical for AI/ML clusters based on advanced computing platforms.
You will have the opportunity to work on all modalities of interconnects connecting GPUs and switches both inside and between data centers, including our primary front and backend networks that train Grok and that customers use for inference. Engineers will own all aspects from design and development to build and operations. You will be expected to define and improve team processes and to contribute to scaling and maintenance efforts.
You will focus on the physical layer and system-level integration of copper (ACC, AEC, CPC) and optical (FRO, LRO/TRO, LPO, AOC, CPO) interconnects that directly determine the performance, power efficiency, scale, and cost of next-generation AI/ML clusters. This is a highly technical, hands-on role bridging ML cluster requirements with cutting-edge interconnect hardware — ideal for engineers who love both large-scale AI systems and the physics/engineering of 200G+ SerDes, PAM4, photonics, signal integrity and diagnostics.
RESPONSIBILITIES
- Design, validate, and productize high-speed copper and optical connectivity solutions for AI clusters (100k+ GPU scale)
- Own vendor due diligence and onboarding for new 1.6T products including AEC and pluggable optical transceivers (DR4/8, FR4) including rigorous bring-up & characterization
- Investigate the opportunity for LPO and LRO in our network
- Evaluate early co-packaged and near-packaged engines for switches and GPUs
- Evaluate and pathfind new interconnect modalities including VCSEL, microLED, THz radio-based solutions to improve network economics and reliability
- Work closely with vendors (transceiver, cable, SerDes, DSP, silicon photonics foundries) to influence roadmaps and ensure timely delivery of next-gen solutions
- Collaborate with ML training teams to translate workload communication patterns into concrete interconnect topology and optical reconfigurability requirements
- Perform system-level simulation of end-to-end fabric performance
- Drive failure analysis, root cause, and corrective actions for interconnect-related issues in production clusters through…